A personal computer has had more and more applications since its functions are improved day by day. No matter for a desktop computer, laptop computer, media center or any further developed computer with a more compact size or more complicated function, nowadays, power consumption is always an issue that the designer should pay attention to.
Conventionally, an Advanced Power Management (APM) specification plays a key role for power management designs. The power managements based on the APM specification are typically performed at a BIOS firmware level, and thus have limitations when applied in modern computer systems. Nowadays, the most popular power management in the art is based on an Advanced Configuration and Power Interface (ACPI) specification, which is performed by way of an operating system of a computer system. According to the ACPI specification, the power management of a computer is implemented with a plurality of power states, for example, including a performance state, a processor state and a sleep state. Generally, in the processor state, the ACPI specification defines the state of a central processing unit as one of the following: C0 (normal operational state), C1 (suspension state), C2 (stop clock state) and C3 (sleeping state). The operating system in the computer system has the CPU selectively enter one of the four states according to the utilization rate of the CPU. In other words, the higher power-saving level the CPU enters, the lower the power voltage is supplied to the CPU so as to reduce power consumption of the computer system to a greater level.
Please refer to FIG. 1A, which schematically illustrating power management means of a conventional computer system. The computer system 1 includes a CPU 10 and a chipset 11 consisting of a north bridge chip 111 and a south bridge chip 112. The CPU 10 communicates with the north bridge chip 111 via a Front Side Bus (FSB) 100. Once the computer system 1 is to enter the processor state, an operating system executed in the computer system (not shown) determines which of the above-mentioned states C0, C1, C2 and C3 should be entered according to the operational condition of the computer system. If the CPU 10 is to enter the C2 or C3 state, the south bridge chip 112 issues a stop clock signal STPCLK (STPCLK#) and a sleep signal SLP (SLP#) to the CPU 10 to lower the data processing rate as well as supplied voltage in order to save power. Furthermore, depending on different power-saving states, the way the south bridge chip 112 asserts the stop clock signal STPCLK and the sleep signal SLP to the CPU 10 may change, as illustrated in FIG. 1B and FIG. 1C. For example, when the state the CPU 10 to enter is the C3 state, i.e. the sleeping state, it means that the CPU 10 should stop all work. Therefore, both the stop clock signal STPCLK and the sleep signal SLP issued by the south bridge chip 112 should be asserted, i.e. switched to at an effective level such as a low voltage level 1121 (FIG. 1C), to assure of the C3 state of the CPU 10. In another example that the CPU 10 is to enter the C2 state which is less power-saving compared to the C3 state, it means that the CPU does not stop working but preserves some power for readily restoring operation. Accordingly, the stop clock signal STPCLK issued by the south bridge chip should be kept asserted while the sleep signal SLP should be de-asserted, i.e. switched to an ineffective level such as a high voltage level (FIG. 1B), in order to be flexible for restoration of power.
As described above, the operating system is used to detect the working condition of the computer system and determine the power-saving state of the CPU according to the ACPI specification. However, other hardware devices cannot timely respond to the update of the state of the CPU. For example, the data transmission rate of a Front Side Bus cannot be adjusted according to the current state of the CPU. Therefore, there is a need to further improve the power management of the computer system.